1. Technical Field of the Invention
The present invention relates to testing ferroelectric memory devices, and particularly to a test circuit and method for testing for effects of degradation of ferroelectric memory cells.
2. Description of the Related Art
Ferroelectricity is a phenomenon which can be observed in a relatively small class of dielectrics called ferroelectric materials. In a normal dielectric, upon the application of an electric field, positive and negative charges will be displaced from their original positionxe2x80x94a concept which is characterized by the dipole moment or polarization. This polarization or displacement will vanish, however, when the electric field returns back to zero. In a ferroelectric material, on the other hand, there is a spontaneous polarizationxe2x80x94a displacement which is inherent to the crystal structure of the material and does not disappear in the absence of the electric field. In addition, the direction of this polarization can be reversed or reoriented by applying an appropriate electric field.
These characteristics result in ferroelectric capacitors, formed from ferroelectric film or material disposed between parallel conduction plates, being capable of storing in a nonvolatile manner a first charge corresponding to a first polarization state in which the direction of polarization is in a first direction, and a second charge corresponding to a second polarization state in which the direction of polarization is in a second direction opposite the first direction. Ferroelectric capacitors are utilized in nonvolatile random access memory devices having a memory cell array architecture that is similar to the memory cell array architecture of dynamic random access memory (DRAM) devices.
In general terms, there are two types of ferroelectric memory cells. Referring to FIG. 1A, a one transistor, one capacitor (1T1C) memory cell utilizes a pass gate transistor T connected between a column line B and a first plate of ferroelectric capacitor C. A second plate of ferroelectric capacitor C is connected to a plate line P. The gate terminal of pass gate transistor T is connected to a word line W. A memory device utilizing a 1T1C memory cell uses a reference memory cell that is accessed at the same time the 1T1C memory cell is accessed so as to provide a charge differential appearing across a pair of column lines coupled to the 1T1C cell and the reference cell. The use of 1T1C ferroelectric memory cells is known in the art.
Referring to FIG. 1B, a two transistor, two capacitor (2T2C) memory cell includes two ferroelectric capacitors C1 and C2. A first pass gate transistor T1 is connected between a first plate of ferroelectric capacitor C1 and a first column line BL of a column line pair. A second pass gate transistor T2 is connected between a first plate of ferroelectric capacitor C2 and a second column line BLxe2x80x2 of the column line pair. A second plate of ferroelectric capacitors C1 and C2 is connected to a plate line P. The gate terminal of pass gate transistors T1 and T2 is connected to the word line W. Each capacitor C1 and C2 stores a charge representative of the polarization state thereof, the charge combining with the charge of the other capacitor to result in a charge differential appearing across column lines BL and BLxe2x80x2 when the 2T2C memory cell is accessed. The polarity of the charge differential denotes the binary value stored by the 2T2C memory cell. The use of 2T2C ferroelectric memory cells is known in the art.
A problem with ferroelectric memory devices is the existence of a phenomenon known as imprint. Imprint is a characteristic of ferroelectric films that refers to the tendency of a ferroelectric film/capacitor to prefer one polarization state over another polarization state. Imprint is known to occur when a ferroelectric capacitor is maintained in a single polarization state for a prolonged period of time. Imprint adversely effects the ability of a ferroelectric capacitor to switch between the polarization states. Consequently, the existence of imprint may directly impact the performance of a ferroelectric memory device.
The performance of ferroelectric memory cells has been seen to degrade over time due to a number of other phenomena as well. For instance, ferroelectric memory cells may be effected by fatigue, retaining data over time, etc. When holding data over a prolonged period of time, such as under accelerated conditions during burn-in, a ferroelectric memory cell may be seen to degrade over the course of several hours or days. FIG. 2 shows how a ferroelectric memory cell may be degraded, with the polarization characteristic being shown for a normal ferroelectric memory cell in continuous set of lines and the polarization characteristic being shown for a degraded ferroelectric memory cell in dashed lines. At some point, a memory cell exhibiting degraded performance may store a charge in its ferroelectric capacitor that cannot be sensed by a sense amplifier, thereby rendering the memory cell incapable of storing data values.
It is inconvenient to accurately test the capability of a ferroelectric memory cell to hold a voltage level using conventional memory read operations, to determine whether a long term reliability risk exists with the memory cell. This is in part due to the fact that both memory read operations refresh the charge stored in the corresponding memory cells. Based upon the foregoing, there is a need to be able to more easily test the soundness of a ferroelectric memory.
The present invention overcomes difficulties with prior test circuits and methods and satisfies a significant need for a test circuit and method for testing the ability of a ferroelectric memory cell to retain a data value. In accordance with an embodiment of the present invention, there is disclosed a ferroelectric memory device having test circuitry therein. The ferroelectric memory device includes an array of ferroelectric memory cells organized into rows and columns. The array includes a plurality of row lines and column lines, with each row line being connected to a row of memory cells and each column line being connected to a column of memory cells. The test circuitry is coupled to the column lines such that when the ferroelectric memory device is configured in a test mode, the test circuitry selectively measures the voltage levels appearing on the column lines and provides externally to the ferroelectric memory device an electrical signal representative of the measured voltage levels.
In particular, the test circuitry senses the voltage level appearing on a selected column line and converts the voltage level to a current level. The test circuitry may include at least one current mirror having a first current leg coupled to the column lines and a second leg coupled to a pad, such as a test pad. A common node between the first and second current legs of the current mirror may also be coupled to another pad, such as a second test pad. When a memory cell is connected to a selected column line, a voltage is created on the selected column line corresponding to the voltage retained in the memory cell. By connecting the first current leg of the current mirror to a selected column line, a current passes through the first current leg in proportion to the voltage appearing on the selected column line. In response, a current passes through the second leg of the current mirror that is in proportion to the current flowing in the first current leg. By sensing the current flow in the second current leg, either by collecting the current on a capacitor or directly sensing the current level, the voltage level appearing on the selected column line may be precisely determined. Once the voltage appearing on the selected column line is precisely known, a determination may be made as to whether the memory cell should be replaced with a redundant memory cell, whether the fabrication process is flawed, etc.